1. Field of the Invention
The present invention relates to a method, an apparatus, and a storage medium for simulating a system using an object oriented language suitable for the simulation of a large scale system such as an SOC (System On a Chip), which includes a plurality of circuit modules, by means of software.
2. Description of the Related Art
There are conventional software simulators using the HDL (Hardware Description Language) for designing a system. Table 1 shows the examples of statements of a circuit model in the HDL, and FIG. 1 is a schematic diagram corresponding to the statement examples of Table 1. Data is input to or output from the circuit module described in the HDL through terminals. The communication between the circuit modules is made by connecting signal lines to the terminals. For example, as shown in FIG. 1 , when a circuit module C includes circuit modules A and B, a terminal a1 of the circuit module A is connected to a terminal b1 of the circuit module B by providing a signal line c1 in the circuit module C ([1] in Table 1), connecting the terminal a1 of the circuit module A to the signal line c1 of the circuit module C ([2]), and connecting the terminal b1 of the circuit module B to the signal line c1 of the circuit module C ([3]). Once the signal line is connected, one of simulation models drives the signal line, and the other simulation model observes the signal value, and thus the signal can be transmitted. To make the communication between the circuit modules accurate, the terminal of one circuit module must be accurately connected to the terminal of the other circuit module.
TABLE 1Statement in HDLModule C;Wire c1, . . .ModuleA A(.a1 (c1), . . .);ModuleB B(.b1 (c1), . . .);Endmodule
A general design procedure for designing a system including a plurality of circuit modules using the software simulator such as the HDL will be explained. First, the system is divided into a plurality of circuit modules. At that time, considering a later step of rejoining the modules, rules of interface between the circuit modules are defined. The rules of interface describe the signal line widths and roles of the terminals of the circuit modules. The rules are described in a document in a natural language, or are orally reported, so that a number of designers have the rules in common. The circuit modules are produced according to the rules.
After all the circuit modules are produced, the system is produced (described) in the HDL to combine the circuit modules so that they can communicate with each other. It is visually judged, or it is checked by system simulation, whether the circuit modules observe the rules. When it is confirmed that the result of the simulation is correct, the actual circuit is produced, based on the HDL statements.
Software simulation using an HDL has been developed to certify small scale circuits or systems. However, there are some problems in the application of this software simulation to SOCs such as LSIs (Large Scale Integrations) having a high integration degree.
For example, when connecting two circuit modules, the functions of the terminals of both the circuit modules must be checked. The conventional simulation using the HDL does not automatically check the functions. Because the terminals can be freely named in the HDL, the names of terminals having specific meanings, such as CLOCK, or RESET, may differ between the circuit modules. Therefore, when connecting the terminals by signal lines, the meanings of the terminals of the respective circuit modules must be visually and manually checked according to the HDL statements or the other documents. Thus, when combining the circuit modules to produce the system, the designers must do the troublesome work to check the connections between the modules.
To connect the circuit modules, the connections of all the terminals of the respective circuit modules must be described. There is the problem that, to change the described connections, a number of portions in the statements must be rewritten. Even when only a clock terminal of a circuit module receives an input, the connections or disconnections of all the terminals of the circuit modules must be described. That is, whenever the connections are changed, the detailed information regarding the circuits to be connected must be rewritten. It therefore requires much labor to replace a circuit module in the system.
A technique of a simulation method, which differs from the software simulation using the conventional HDL, and which is suitable for the development of a system including a plurality of modules, is disclosed in the reference “OO-VHDL Object-Oriented Extensions to VHDL” (IEEE Computer, October, 1995, pp. 18-26). The simulation method described in the reference uses a new language in which the features of an object oriented language are incorporated into the conventional HDL, and describes the modules and the connections between the modules. The reference describes that the features of the object oriented language, such as “class” and “inheritance”, make the statements and recycling of the modules easy. The reference, however, does not disclose a specific means for applying the simulation method, or the method for describing the modules to a large scale system in which a plurality of various types of circuit modules are connected.
The reference “C++ Simulator [ClassMate] for Actualizing Prior Certification of SOC (the Institute of Electronics, Information, and Communication Engineers, the Technical Report, VLD98-46, 1998-09) discloses a method for the simulation of large scale systems using the C++ language which is an object oriented language. The simulation method and the method for describing the modules, however, do not make use of the advantages of the object oriented language. Therefore, there remains a problem similar to that of the HDL in the recycling of the modules and the connections between the modules.